The present invention relates to a semiconductor device and, specifically, to a semiconductor device having a plurality of standard cells.
As the performance of a semiconductor device is becoming higher and higher, efforts are being made to reduce the size and increase the integration of the semiconductor device. To obtain a small-sized highly integrated semiconductor device, layout design for achieving a smaller cell width and a smaller cell height is becoming the mainstream in this field. In the case of SRAM (Static Random Access Memory) which is a type of volatile memory, like an integrated circuit disclosed by Japanese Unexamined Patent Publication No. 2009-130238 (Patent Document 1), linear load transistors and active regions are inclined at a certain angle with respect to the extension direction of standard cells in a plan view. This structure provides high integration as compared to an integrated circuit in which all of the above load transistors and active regions are not inclined in the extension direction of the standard cells, thereby reducing the size of the standard cells.